A parallel processor network includes several identical processors (cells) that are arranged in a regular form. Each cell has an income signal, a dynamic state and an outcome signal.
The idea in a parallel processor network for processing images is that one processor (cell) corresponds to one pixel, and therefore, it is possible to provide a parallel processor network that is able for very fast processing (in theory). A problem for integrating this kind of a parallel processor network into a chip is that the size of processors have not been minimized to enable implementing integration of tens or hundreds of thousands of processors into a chip without lowering the liability.
In a parallel processor network, the cells are connected to their neighboring cells (they can also be connected for example to all other cells in a parallel processor network), i.e., they affect to a dynamic state of their neighboring cells. This affect correlates straightforwardly to the income of the cell and its own dynamic outcome. These features enable a real-time signal processing, because the data processing occurs in all cells at the same time.
A parallel processor network can be implemented for processing images, e.g. for filtering salt & pepper noise from an image. There has been presented several methods for filtering noise from image, wherefrom one of the generally used methods is median filters. A median filter is a special case of a ranked-order filter in which a median of the numbers can be chosen, but also any other ranked-order number unit can be chosen. These cases include for example finding a maximum or a minimum from a specified array of numbers. The operations, which use a method based on finding a maximum or a minimum from the specified array of numbers, are widely used in image processing, e.g., when mathematical morphology operations are implemented.
One special case of ranked order filtering is median filtering e.g., the fifth largest current out of nine currents is extracted. An extension to the basic median filtering is described e.g., in L. Yin, R. Yang, M. Gabbouj and Y. Neuvo, “Weighted Median Filters: A Tutorial”, IEEE Transaction on Circuits and Systems—II, Vol. 43, pages 157-192, 1996, where each input can be given different weights to favor the selection of certain variables. In this weighting scheme a weight of a magnitude e.g., three assigned to a certain variable means practically that the variable is entered three times to the list of variables out of which the median is selected. This also means that the total number of variables out of which the selection is to be made has increased by two.
There has been described some analog implementations for filtering images. In an article by G. Fikos, S. Vlassis, and S. Siskos, “High-Speed, Accurate Analogue CMOS Rank Filter”, Electronics Letters, Vol. 36, No. 7, pages 593-594, 2000, there is proposed a current-mode rank extractor in which a circuit is suitable for multiple inputs. Furthermore, the extracted rank is selectable, i.e., the rank filtering involves the selection of the kth largest current I(k). A basic cell of the implementation is a current comparator, which has an output current. The basic cell contains two different building blocks, one to perform the actual comparison and one to provide the current output. The current output of the basic cell is realized by complementary current sources, i.e., one source provides positive output currents and the other provides negative output currents, with switches at their outputs. The magnitudes of the output currents of these current sources are assumed to have equal magnitudes inside one basic cell, and also within the whole system. Thus the system is not able to perform weighted ranked order filtering. The output switches are controlled by a voltage that is generated inside the basic cell by a current comparator with voltage output. A plurality of basic cells provide their current output to a common node where the sum of the output currents is compared to another current. This another current is generated by a current source that must be able to provide both positive or negative currents, one polarity at the time, and by controlling the magnitude and sign of this particular current source input currents to the system that have a predetermined ranked order can be extracted.
The analog implementations for processing images described in prior art do not allow programmable function or they are too complex to be integrated into a chip in large numbers of processors. Some of the structures described in prior art also have essentially high power consumption, and therefore, it is not preferred to integrate thousands of processors into a chip.